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| Research and Development of Deployable IV&V Methods for FPGA Applications | |
| Point of Contact |
Scott W. Schield scott.schield@ivv.nasa.gov |
| Dates | June 2006 - May 2007 |
| Problem | The objective of this research project is to define independent verification and validation (IV&V) of FPGAs and develop the methods and tools to accomplish the tasks. The project will begin by surveying the present applications of FPGAs, focusing on aerospace applications. The survey will function as a knowledgebase that analysts use to familiarize and prepare for a task but also function as a repository for lessons learned. In the context of this project the knowledge will be used to define the FPGA IV&V. Methods will be developed to guide the IV&V analyst through each phase of analysis. Approaches to performing IV&V will differ depending on the development phase at which design (concept, requirement and design) and implementation artifacts are released to IV&V. This project will consider each scenario and determine which IV&V tasks are practical and effective. The project will implement tasks and methods on one or more FPGA applications, supported by verification and simulation tools and compare the results to pre-established IV&V goals. Finally, this R&D project will provide Criticality Analysis based on implementation experience and estimates of associated IV&V tasks on FPGA applications. |
| Objective | The high-level objective of this two-year research project is the development of goals, methods, and tools for complete life cycle IV&V of FPGAs. To meet this objective, several sub-objectives must first be met. First, a survey of FPGA applications will be performed and then used to create a repository or knowledgebase. The repository will be made public to NASA and NASA subcontractors and be updated based on their experiences. The next objective will be to identify and document approaches to performing IV&V for each development phase (concept, requirement and design) and artifact released to IV&V during development. Next, the project will implement methods and simulation tools supporting IV&V goals on one or more FPGA applications. The project will select one or more FPGA designs for testing and refining the techniques, including tool recommendation and selection. It is complementary to the existing NESC FPGA R&D project that focuses on static analysis of VHDL/Verilog code. These objectives will lead to achievement of the overall objective of producing goals, methods, and tools for complete life cycle IV&V of FPGAs.By the end of the second year (March 2008, assuming a March 2006 start), proven IV&V techniques for full-lifecycle IV&V analysis will be established. |
| Results |
SAS 06 Executive Presentation.ppt SAS 06 Technical Presentation.ppt READ_ME_for_FPGA_Knowledge_Base_zip.docx FPGA Knowledge Base.zip FPGA IV&V Methods and Applicable Approaches.doc |
| Keywords | programmable logic,software assurance, quality assurance, safety assurance, safety studies, software and hardware hybrids, complex electronics, verification, validation, FPGA, field programmable gate array, PLD, FPGA |
| Categories |
Quality Assurance Quality Control Quality Engineering Criticality Analysis Domain-Specific Analysis |
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Curator: Josh Stonestreet NASA Official: Lisa Montgomery |
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